1. Field of the Invention
This invention is related to the field of processors and, more particularly, to address generation for memory array access in processors.
2. Description of the Related Art
Processors generally include the ability to generate memory addresses, including fetch addresses from which instructions are read to be executed in the processor and data addresses from which operands are to be read. Typically, the address generation includes adding one or more values to produce the address. The addresses are large, such as 32 bits and up to 64 bits currently, and can increase in the future. Thus, the addition can take a fairly long time, especially when viewed in the context of a high frequency processor's short cycle time.
The time to generate the address is often particularly important when it is part of an access to a memory array within the processor, such as a cache, cache tag, or translation lookaside buffer. The timing path from receiving the operands, generating the address, decoding the address, and accessing the memory array is frequently one of the most critical timing paths in the processor.